The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device driving current improvement becomes more important. Metal-oxide-semiconductor (MOS) transistor current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance and increasing carrier mobility can improve the transistor current performance. Gate length reduction is an ongoing effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing gate dielectric thickness, increasing gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. Stress, sometimes referred to as strain, can enhance bulk electron and hole mobility. The performance of a MOS transistor can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
FIG. 1 illustrates a variation of an NMOS transistor such as described in U.S. patent application Ser. No. 11/115,484, which is incorporated herein by reference. The NMOS transistor includes a SiGe layer 2 on a semiconductor substrate 10, and a silicon layer 4 on the SiGe layer 2. Due to mismatched lattice constants between SiGe layer 2 and silicon layer 4, an inherent tensile stress is developed in silicon layer 4 and an inherent compressive stress is developed in SiGe layer 2. The channel region in the silicon layer 4 is thus tensile-stressed. Free surfaces 6 allow the development of high stresses when the Si/SiGe layers are annealed. FIG. 1 also includes silicide regions 12, which are not included in U.S. patent application Ser. No. 11/115,484.
The transistor shown in FIG. 1 has high performance due to a highly stressed channel region, particularly when formed using 90 nm technology and above. However, if this embodiment is to be used for future-generation integrated circuits, such as integrated circuits manufactured using 65 nm or 45 nm technology, shallower junctions will cause current crowding effects in narrow regions 14, which are close to corners of the respective silicide layers 12. The current crowding effects result in increased external resistance and can severely degrade the performance of the transistors. For example, for integrated circuits fabricated using 65 nm technology, drive current Ion of transistors may be degraded by about 12 percent or more due to current crowding effects. This at least partially offsets the benefit introduced by a stressed channel region. Leakage currents between the silicide regions 12 and substrate 10 also increase due to a short distance D1 between silicide regions 12 and substrate 10.
Therefore, there is a need for a novel method suitable for forming future-generation integrated circuits, so that increasingly shallower junctions can be formed without causing significant current crowding effects and leakage currents.